1. Field of the Invention
The present invention generally relates to a semiconductor device, in particular, to a chip package structure having a circuit pattern.
2. Description of Related Art
In the semiconductor industry, the fabrication of integrated circuits (ICs) mainly comprises three phases: IC design, IC process, and IC package.
In the fabrication of an IC, a chip is fabricated through wafer process, IC formation, and wafer sawing etc. A wafer has an active surface which generally refers to the surface of the wafer having active devices. After the IC in the wafer is completed, the active surface of the wafer is further disposed with a plurality of bonding pads, so that those chips eventually formed by sawing the wafer can be electrically connected to a carrier through these bonding pads. The carrier may be a lead frame or a package substrate and may have a plurality of contacts. A chip can be connected to the contacts through wire bonding or flip chip bonding so that the bonding pads of the chip can be electrically connected to the leads to form a chip package structure.
While bonding the bonding pads and the contacts through bonding wires, the electrically connected bonding pads and contacts usually have to be located at the same side of the chip in order to shorten the bonding distance. Accordingly, the dispositions of the bonding pads and the leads are restricted and the circuit layout becomes inflexible. Besides, since the leads and the chip are connected only by the bonding wires, the heat produced by the chip cannot be effectively conducted to the surroundings, therefore the heat dissipation performance of the chip package structure is not satisfactory.